VHDL 93 Reference Update

The introduction of VHDL 93 brought a number of significant and useful features to the expressive power of VHDL. The key additions and changes are listed here with more detailed explanations in the sections following:

The most visible change - statement bracketing
The syntax used to bracket entities, components, processes etc, is now consistent, as shown below...

  entity Name is
    ...
  end entity Name;

  architecture Name of EntityName is
    ...
  begin
    ...
  end architecture Name;

  configuration Name of EntityName is
    ...
  end configuration Name;

  package Name is
    ...
  end package Name;

  package body Name is
    ...
  end package body Name;

  component Name is
    ...
  end component Name;

  procedure Name is
    ...
  begin
    ...
  end procedure Name;

  function Name return Mark is
    ...
  begin
    ...
  end function Name;

  Label: process (...) is
    ...
  begin
    ...
  end process Label;

  Label: ... generate
    ...
  end generate Label;

  Label: if ... then
    ...
  end if Label;

  Label: case ... is
    ...
  end case Label;

  Label: ... loop
    ...
  end loop Label;

  type Name is record
    ...
  end record Name;

The VHDL 93 syntax is upwardly compatible with the VHDL 87 syntax so the new keywords, names and lables may be omitted.

The most significant change - direct instantiation
Design entities can now be instantiated directly, rather than indirectly via components. Thus, a design hierarchy can be described without needing to write any component declarations or configurations! The new syntax for instantiation is...

  Label: component CompName       port map (...);
  Label: entity EntName           port map (...); 
  Label: configuration ConfigName port map (...);

For example, to instantiate a entity BLOCK_1 on the working library...

  G1: entity work.block_1 (rtl) port map (A, B, F);

Also the rules for configuration have been clarified such that an empty configuration declaration is unnecessary to force default configuration.

The incompatible change - file declarations
The new syntax for file declarations is incompatible with VHDL 87. This means that any code using TEXTIO must be re-written...

    file F : TEXT is "NAME";                    -- VHDL 87 or 93
    file F : TEXT is in  "NAME";                -- VHDL 87 only
    file F : TEXT is out "NAME";                -- VHDL 87 only
    file F : TEXT open READ_MODE   is "NAME";   -- VHDL 93
    file F : TEXT open WRITE_MODE  is "NAME";   -- VHDL 93
    file F : TEXT open APPEND_MODE is "NAME";   -- VHDL 93
    file F : TEXT;                              -- VHDL 93

Explicit file open and file close procedures are provided too, so that you can be explicit about when a file is opened or closed...

  file_open (status,        -- out open_ok | status_error |
                            -- name_error  | mode_error
             F,             -- the file
             External_name, -- in String
             Open Kind);    -- in READ_MODE | WRITE_MODE |
                            -- APPEND_MODE
  file_close(F);

The most controversial change - shared variables
Variables may be shared between processes, and thus used for inter-process communication. Variables declared outside processes must include the keyword shared, for example...

  shared variable V : Integer;

However, any non-trivial use of shared variables is illegal in VHDL 93 ! A supplementary standard 1076a defines how shared variables my be used.

Other useful changes - new attributes
There are several new pre-defined attributes, including...

T'IMAGE(X) 

Wher T is a scalar type. Returns the value of X represented as a string. Really useful for writing out values of user defined types to a text file.

T'VALUE(X) 

The inverse of T'IMAGE, and thus useful when reading in text files.

T'ASCENDING 

TRUE if and only if the range of the type T is ascending. Useful for writing utility subprograms that operate on vectors.

E'PATH_NAME 

Where E is anything. Full hierarchical p[ath name of the item (e.g., "ent:comp:comp:sig"). Useful when writing out messages.

There is a new attribute defined in package STANDARD...

  attribute FOREIGN : String;

This attribute may be attached to an architecture or a subprogram to indicate that it is foreign (i.e., defined outside VHDL)

The report statement
In VHDL 87, one frequently writes something like this...

  assert FALSE report "Simulation finished with no errors.";

A new statement is provided in VHDL 93 to make the assert FALSE bodge unnecessary...

  report "Simulation finished with no errors.";

New operators
There are seven new built-in operators...

  xnor               -- defined on Boolean, Bit, Bit_vector
                     -- Std_logic, Std_logic_vector
  sla sll sra srl    -- Shift left or right, logical or arithmetic
  rol ror            -- Rotate left or right, left operand is a
                     -- vector, right operand is an Integer.

Bit string literals
Values of types such as std_logic_vector can now be written in hexadecimal or octal, as well as binary strings of 0's and 1's. For example...

  "100_111"   = O"47"
  "1010_1111" = X"AF"

Conditional signal assignments
The else branch may be omitted from a conditional signal assignment, and both conditional and selected signal assignment statements can use the keyword unaffected to uindicate that the output is unchanged. Thus it is now possible to describe latches and flip-flops using short concurrent statements, for example...

  Flipflop: Q <= D when Rising_edge(clock);
  Latch:    Q <= D when Enb = '1'; 
  Counter:  Q <= unaffected when Hold = '1' else Q + '1';

Specialised changes
VHDL 93 contains many highly specialised or obscure changes, some of which are listed below...
For inertial delay mode, the pulse rejection region can be defined independently of the delay for example...

  F <= reject 5 ps inertial A nand B after 10 ps;

Processes can be postponed such that they only execute immediately before simulation time is advnaced, i.e., after all signals have settled to a steady value within each time step. This is usefu when checking for illegal combinations of signal values, because glitches that occur at intermediate delta times are ignored.

Functions can be declared to be impure or pure. Impure functions may have side effectes (changing the values of extwernal variables), whereas pure functions do nothing but return a vlue. For example...

  impure function RANDOM return REAL;

A generate statement may contain a declaration as well as statements This waas added so that configuration specifications may be used for example...

  for i in 0 to 7 generate
    for all: Comp use entity Lib.Comp;
  begin
    L: Comp port map (...);
  end generate G;

Aliasing is generalised such that anything can be aliased. For example...

  alias "nand" is
    IEEE.Std_logic_1164."nand" (Std_logic, Std_logic) return Std_logic;

Groups of VHDL constructs can be defined to pass information through to downstream tools, for example...

  group PinToPin is (signal, signal);
  group G1 : PinToPin (Clock, Q);

All statements can now be labelled, including sequential statements.

Extended identifiers allow any printable character to be included in a name. Extended identifiers start with a backslash and end with a backslash, for example...

  \A.$%^&*()\    -- Hey, guys! This is NOT Awk!

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