Levels of Abstraction

VHDL can be used to describe electronic hardware at many different levels of abstraction. When considering the application of VHDL to FPGA/ASIC design, it is helpful to identify and understand the three levels of abstraction shown opposite - algorithm, register transfer level (RTL), and gate level. Algorithms are unsynthesizable, RTL is the input to synthesis, gate level is the output from synthesis. The difference between these levels of abstraction can be understood in terms of timing.

Levels of abstraction in the context of their time domain

Algorithm
A pure algorithm consists of a set of instructions that are executed in sequence to perform some task. A pure algorithm has neither a clock nor detailed delays. Some aspects of timing can be inferred from the partial ordering of operations within the algorithm. Some synthesis tools (behavioural synthesis) are available that can take algorithmic VHDL code as input. However, even in the case of such tools, the VHDL input may have to be constrained in some artificial way, perhaps through the presence of an ‘algorithm’ clock — operations in the VHDL code can then be synchronized to this clock.

RTL
An RTL description has an explicit clock. All operations are scheduled to occur in specific clock cycles, but there are no detailed delays below the cycle level. Commercially available synthesis tools do allow some freedom in this respect. A single global clock is not required but may be preferred. In addition, retiming is a feature that allows operations to be re-scheduled across clock cycles, though not to the degree permitted in behavioural synthesis tools.

Gates
A gate level description consists of a network of gates and registers instanced from a technology library, which contains technology-specific delay information for each gate.

Writing VHDL for Synthesis
In the diagram above, the RTL level of abstraction is highlighted. This is the ideal level of abstraction at which to design hardware given the state of the art of today’s synthesis tools. The gate level is too low a level for describing hardware - remember we’re trying to move away from the implementation concerns of hardware design, we want to abstract to the specification level - what the hardware does, not how it does it. Conversely, the algorithmic level is too high a level, most commercially available synthesis tools cannot produce hardware from a description at this level.

In the future, as synthesis technology progresses, we will one day view the RTL level of abstraction as the “dirty” way of writing VHDL for hardware and writing algorithmic (often called behavioural) VHDL will be the norm.

Until then, VHDL coding at RTL for input to a synthesis tool will give the best results. Getting the best results from your synthesizable RTL VHDL is a key topic of the Doulos Comprehensive VHDL and Advanced VHDL Techniques training courses. The latter also covers behavioural synthesis techniques.

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