Bus/Interconnect Models

Bus and Interconnect Models

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RASSP Processor Modeling Effort at Georgia Institute of Technology: Point of Contact: Dr. Vijay Madisetti; Form to request information on licensing GTRC models; Processor Architectures; General Taxonomy Level : Behavioral, Full Functional; Created by : Georgia Institute of Technology/ Digital Signal Processing Laboratory
Intel 8251 USART: Description : Intel 8251 Universal Synchronous/Asynchronous; Receiver/Transmitter (USART); General Taxonomy Level : Full Functional; Created by : Indraneel Ghosh (University Of California, Irvine)
UART Receiver -- a VHDL file: Description : Models the receive portion of a UART; General Taxonomy Level : Behavioral; Created by : Ben Cohen, VhdlCohen@aol.com
UART Transmitter -- a VHDL file: Description : Models the transmit register of a UART; General Taxonomy Level : Behavioral; Created by : Ben Cohen, VhdlCohen@aol.com
VME Bus Model -- a compressed tar file: Description : This VME bus model is designed to allow test vectors; to be input on a separate set of signals, which then operate the; the VME bus. NOT thoroughly tested.; General Taxonomy Level : Behavioral; Created by : Tom Rust and Don Day (RGB Spectrum); Email: tom@rgb.com, don@rgb.com
VME Bus Model (Here): Description : ERC32 VMEbus Interface (EVI32); Specification and synthesizable VHDL model; General Taxonomy Level : Synthesizable RTL; Created by : European Space Agency

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