ERC32 VMEbus Interface (EVI32) - specification and synthesizable VHDL model
The EVI32 is a 32-bit VME interface circuit designated to interface the
ERC32 processor chip set to the VMEbus. The EVI32 fully adheres to the
IEEE 1014-1987 VMEbus standard, and is compatible with the commercial VMEbus
specification. EVI32 can act as a system controller and provides both master
and slave interfaces.
EVI32 comprises the following functions:
A32/A24/D32/D16/D8 master and slave interface;
Interrupt handler;
Interrupter;
Single level arbiter (SGL);
VME bus timer;
Optimised D16 interface;
Four mailboxes for multi-processor communication;
Minimised usage of external buffers;
The EVI32 specification and VHDL design is a result of an internal ESTEC
development. The design has been implemented in an FPGA and is suitable
for implementation in radiation hard or tolerant ASIC technologies.
The functional specification is available in Adobe PDF format at:
The file can also be decompressed under MS-Windows using WinZip or similar
tools. For information regarding availability and usage of the VHDL model,
and the password for the ZIP file, please contact Jiri Gaisler (ESTEC/WS)
via e-mail: jgais@ws.estec.esa.nl
