Instruction Dispatch by CRS (clock 3)
| Status | Dst | Op1 | V | Op2 | V
0 | Full | 0 | 0 | T | 25 | T
1 | Full | 1 | 0 | F | 30 | T
2 | Full | 2 | 1 | F | 50 | T
3 | Full | 3 | 2 | F | 1 | F
4 | Empty | 0 | 0 | F | 0 | F
Tail points to oldest entry. Start at tail, and look for entries that have both operands valid. ONLY entry #0 (instruction A) has both operands valid. Dispatch this entry to the execution units.
Issued Instructions which are accepted from DRR by CRS can be dispatched by CRS in the same clock cycle.