Fighting the Memory Latency Battle

• The Tera MTA addressed high memory latency via its multi-threaded architecture

  • A high-risk, uncoventional approach; addresses both instruction and data fetches
  • Could have high benefits

• External Memory access penalty continues to grow

  • Memory bandwidth not keeping track with processor speeds.

• Architectural approaches try to hide the memory latency

• Memory manufacturers are trying to make memory interface faster

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