Memory Consistency
Recall the shared bus ‘Write-Invalidate’ protocol
- If processors A, B,C had the same cache line, in state ‘Shared Clean’, when Processor A wrote to the cache line, an Invalidation transaction was sent to B, C and the cache line went to Exclusive Modified
On a single shared bus system, all processors see the invalidation transaction at the same time
What about in a scalable multiprocessor using an interconnection network?
- Memory transactions can be seen at different times by processors depending on location of processor