Superscalar Processors

• Goal is to execute an arbitrary instruction stream and to achieve a clocks per instruction (CPI) of < 1.0

  • Usually, all instruction streams are ‘legal’ since the instruction set architecture may have been previously implemented on non-superscalar architectures and thus legacy codes must be executed.
    • If the Instruction Set Architecture (ISA) has been designed from the beginning to be implemented on a super scalar architecture, then have the freedom of defining what a legal code stream is.
  • Current state of the art Superscalar processors implement 2-4 instructions per clock

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