Straight Line Dependencies (cont)
i1: mul r1, r2, r3; r1 <= r2 * r3 i2: add r1, r4 , r5; r2 <= r4 + r5
If instruction i1 (mul) finishes AFTER instruction i2 (add), then register r1 would get the wrong value. Instruction i1 could finish after instruction i2 if separate execution units were used for instructions i1 and i2.
One way to solve this hazard is to simply let instruction i1 proceed normally, but disable its write stage.