Add a pipeline stage

DFF

LOGIC

DFF

Tpd/2

Clk Freq = 1/ (Tclk2q + Tpd/2 + Tsu)

InA

InB

InC

InD

OutA

OutB

DFF

Tpd/2

LOGIC

Latency = 2 clks

Previous slide

Next slide

Back to first slide

View graphic version