Speeding up the Clock

• The register-to-register delay is usually the delay path that sets the maximum clock rate

• From a design point of view, can only affect the combinational logic between the registers

  • Need to shorten the maximum combinational delay path
  • Setup/Hold time of registers are fixed

• Can shorten the delay by placing a register in the combinational logic to break longest delay path

  • This technique is called pipelining
  • Adds latency to the output (the number of clocks between an input value and its corresponding output result)

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