Muxes

Lots of different ways to do muxes in VHDL. The muxbad example uses if statements - this may not synthesize as well as using either the CASE or SELECT statements.

For Altera, the synthesis results were:

Mux (CASE statement - sequential) - 24 Logic CellsMux (SELECT statement - concurrent) - 24 Logic CellsMux (If-else statement) - 27 Logic cells

With the CASE or SELECT statements, the synthesis can assume a mux structure. With the If-Else construct, a priority chain is first assumed, which may simply to a mux implementation based on the conditions being tested.

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