This short tutorial discusses use of the Logic Synthesis service implemented via the Viewlogic VHDLDES tool. This service is setup to synthesize VHDL files to FPGA libraries used by MSU ECE classes (X4000, Altera, Actel).
Much of the power of the Viewlogic synthesis environment is NOT exposed via this GUI; the intended use of this GUI is for routine, quick synthesis experiments.
You will need the following input file(s) for this tutorial:
The main window for the Viewlogic VHDLDES logic synthesis service is shown
below:
The various fields in the service window must be filled in before a job can be submitted to the server. The fields are explained below.
Left clicking on the VHDL File button will pop up a file dialog box thru which you can specify your input file. Alternatively, you can use the typein field to specify the pathname to your VHDL file.
Use this choice menu to to specify the target technology for the synthesis operation.
Use this typein field to specify the name of the TOP-LEVEL design entity in your input file. If the design file is VHDL and only contains one entity/architecture pair, then the design name should match the entity name (NOT the file name!). If there is more than one entity/architecture in the input file, then it should match the name of the TOP-LEVEL entity.
Specify an optional 'synth.ini' file which can further customize the synthesis operation. See Viewlogic documentation for more information.
This choice-menu provides a yes/no option; if no optimization is done then only mapping is done to the target technology without a further optimization against constraints.
This typein field allows a maximum delay to all outputs constraint to be specified.
This choice menu allows you to provide a hint to the synthesis operation as to what type of design is being synthesized (datapath, fsm, etc). The default choice works ok for most designs.
This typein field allows a user to specify an delay package to be included with the VHDL file during parsing.
This typein field allows a user to specify an optional timing file to be used for the target technology instead of the default for that technology.
This no/yes choice menu is only for use with the Xilinx technology; it optionally includes the Xilinx outpads in the resulting wir file.
Left clicking on this button will pop up a dialog box thru which you can specify output directory. Alternatively, you can use the typein field to specify the pathname to your directory. The directory will be created if it does not exist; files which already exist in the directory will be overwritten upon completion of the job.
During job execution a status window will appear which will allow you to monitor the progress of the job execution. At this point there is no way for the user to interact with the job during execution (we want to add at least a 'kill' button in the near future).
When the job is complete, the directory specified in the 'output directory' will contain the results files of the synthesis run. A README file in this directory explains what each result file contains.
Run the Synopsys synthesis service using the 'dec3to8.vhd' file referenced above as the input file. The other choices should be (if a choice is not listed then use the default as given by the GUI)
These options will cause the synthesis tool to use a minimum area constraint during synthesis. Once the above choices have been set, click on the 'Run' button. You should see a log window appear which shows the progression of the synthesis run. When the job is finished, you can look in the 'results' directory for the result file which will be called "wir/dec3to8.1". The file "dec3to8.rpt" will provide a report of the synthesis operation results.
It is important to realize that your input file is transferred to the server before synthesis, and all result files are transferred back to your local output directory. If you are using a dialup link and are using large input/output files, then this transfer may take a long time.
Warning: The arbiter and blackjack examples in the Synopsys tutorial do not work with VHDLDES.