library IEEE;
use IEEE.std_logic_1164.all;

--*************************************************************************
-- IO Interface Declaration
--*************************************************************************

entity reg8bit is
port
(
-- inputs
  signal  clk:               in  std_logic;
  signal  reset:             in  std_logic;
  signal  load:              in  std_logic;
  signal  din:               in  std_logic_vector(7 downto 0);
  signal  dout:              out  std_logic_vector(7 downto 0)
);
end reg8bit;

architecture behavior of reg8bit is
signal n_state,p_state : std_logic_vector(7 downto 0);
begin

dout <= p_state;

comb: process(p_state,load,din)
begin
  n_state <=p_state;
  IF (load='1') THEN  n_state <= din;  END IF;
end process comb;

state: process(clk, reset)
begin
if (reset = '1') then  p_state <= "00000000";
elsif  (clk'event and clk = '1') THEN
   p_state <= n_state;
 END IF;
end process state;


end behavior;