-- Model Name : Reduced Activity - Parwan ALU
-- Author : Zainalabedin Navabi
-- Last Updated : 09 / 15 / 1996
-- This document is © copyrighted by the Author.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--
LIBRARY EXEMPLAR;
USE EXEMPLAR.exemplar_1164.ALL;
--
LIBRARY WORK;
USE WORK.synthesis_parameters.ALL;
USE WORK.synthesis_utilities.ALL;
USE WORK.global_environment.ALL;
USE WORK.alu_operations.ALL;
--
ENTITY arithmetic_logic_unit IS
PORT (code : IN std_logic_vector (2 DOWNTO 0); alu_operate : IN std_logic);
END arithmetic_logic_unit;
--
ARCHITECTURE synthesizable_behavioral OF arithmetic_logic_unit IS
BEGIN
coding: PROCESS (alu_operate)
VARIABLE t : std_logic_vector (9 DOWNTO 0);
VARIABLE v, c, z, n : std_logic; --in_flags 3210
BEGIN
CASE code IS
WHEN a_add_b | a_sub_b =>
t := addsub_cv (ac_out, dbus, sr_out(2), code(1));
c := t(8); v := t(9); -- other flags are set at the end
WHEN a_and_b =>
t := "00" & ( dbus AND ac_out );
c := sr_out(2); v := sr_out(3);
WHEN a_input =>
t := "00" & dbus;
c := sr_out(2); v := sr_out(3);
WHEN b_input =>
t := "00" & ac_out;
c := sr_out(2); v := sr_out(3);
WHEN b_compl =>
t := "00" & ( NOT ac_out );
c := sr_out(2); v := sr_out(3);
WHEN OTHERS =>
t := "0000000000"; c:= '0'; v := '0';
END CASE;
n := t(7);
z := NOT all_or (t(7 DOWNTO 0));
alu_out := t (7 DOWNTO 0);
alu_flags := v & c & z & n;
END PROCESS coding;
END synthesizable_behavioral;