Description
A significant improvement can be done in simulation speed by using the right modeling styles. For example, replacing bus signals with shared variables will definitly improve the simulation speed. If such steps are taken, other parts of a VHDL code must be adjusted to conform with such changes. Together, a combination of techniques, after they are applied to a VHDL model, are refered to as "coding styles". We have developed several coding styles for improving simulation performance. The styles are defined such that automatic transformation from a standart RT level description is possible into our optimized code.
Reduced Activity
Simulation speed can be improved by suppresing activities in data and control parts of a hardware model.
Concurrency
Accesing data in a burst, and concurrent processing of data can result in significant improvement in processing vectored data.
Application to RTL Description
All our techniques and styles are applied to standart RT level descriptions.