Reduced Activity
Description
Signals in VHDL simulation are costly. Signal events cause resolution functions to be called, scheduling to be done, and timing to keep track of. When a register is clocked, signal activities occur inside a register and then out on the register output, which may cause more signal activities on busses that it drives. Between placing differeent values on a bus, the Z value on each bit of a bus causes further events. Not all activities result in values that are significant, or are atored in a register. Nevertheless. all these activities cost simulation time.
Reduction or suppresssion of activities for better simulation performance has been addresed in conjunction with event driven simulation [Earnst Ulrich]. In our VHDL modeling, we present description styles that will eliminate activities in data part and controller of an RT level hardware description.
Reducing Data Activity
Bus activities can be eliminated when buses are repleced by shared variables.
Reducing Control Activities
To eliminate activities due to control signals, data actions have to take place in a specific order.
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