See Also

The Quartus^® II software can infer RAM from a suitable description in a Verilog Design File (.v). This feature can be used to implement RAM in a Verilog HDL design, and is an alternative to implementing a RAM using an Altera-provided megafunction (which is described in Implementing CAM, RAM and ROM). RAM inference is controlled by the Auto RAM Replacement logic option, which is turned on by default.

The Quartus II software recognizes single-port and simple dual-port RAM. True dual-port or quad-port RAM cannot be inferred and must be instantiated using a megafunction. RAM will only be inferred for target families that have appropriate RAM blocks. No RAM will be inferred for devices without RAM blocks. Similarly, if the Verilog Design File describes an asynchronous RAM, no RAM will be inferred when the target family has RAM blocks that do not support an asynchronous mode.

The example below shows ram_single.v, a Verilog Design File that implements a 128 x 8-bit synchronous single-port RAM with common read and write addresses:

module ram_single(q, a, d, we, clk);

   output[7:0] q;
   input [7:0] d;
   input [6:0] a;
   input we, clk;
   
   reg [7:0] q;
   reg [6:0] read_add;
   reg [7:0] mem [127:0];
  
   always @(posedge clk) begin
      if (we)
            mem[a] <= d;
         read_add <= a;
   end
 
   assign q = mem[read_add];
 
endmodule

The example below shows ram_dual.v, a Verilog Design File that implements a 128 x 8-bit simple dual-port RAM with separate read and write clocks. When the Quartus II software infers a RAM block for a memory with separate read and write clocks, the functionality of the design will change slightly. The behavior when reading and writing to the same address will be different. When the functionality of the design changes, the Quartus II software issues a warning message to alert the user and describe the changes.

module ram_dual(q, addr_in, addr_out, d, we, clk1, clk2);

   output[7:0] q;
   input [7:0] d;
   input [6:0] addr_in;
   input [6:0] addr_out;
   input we, clk1, clk2;
 
   reg [6:0] addr_out_reg;
   reg [7:0] q;
   reg [7:0] mem [127:0];
 
   always @(posedge clk1) begin
      if (we)
         mem[addr_in] <= d;
   end
 
   always @(posedge clk2) begin
      q <= mem[addr_out_reg];
      addr_out_reg <= addr_out;
   end
	
endmodule

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