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A latch can be implemented implicitly with Conditional ("If-Else") Statements that have not been completely specified. The Conditional Statement must be inside an Always Construct that is not sensitive to a posedge or negedge clock.

The example below shows a Verilog Design Files (.v) that includes an Always Construct with a Conditional Statement that is not completely specified.

module latchinf (enable, data, q);

   input  enable, data;
   output q;
   reg    q;

   always @ (enable or data)
      if (enable)
         q <= data;

endmodule

In the example above, the circuit analyzes the value of the enable signal. If enable equals 1, the value data is assigned to q. If enable equals 0, the circuit maintains its previous state, creating a latch.

For more information, see the following sections of the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual:

• Section 9.2: Procedural Assignments
• Section 9.4: Conditional Statements
• Section 9.7.2: Event Control
• Section 9.9.2: Always Constructs

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