See Also

An Always Construct with an Event Control can be used to create combinatorial logic if the construct has the following properties:

• The Event Control for the construct is not sensitive to a rising or falling edge (i.e., posedge or negedge) of a clock.

• The Event Control for the construct is sensitive to any possible change in the output of the construct, i.e., it contains every variable whose change in value causes the value of one or more Procedural Assignments in the construct to change, and therefore may cause the output of the construct to change.

• The Always Construct provides an output for every change or combination of changes in the Procedural Assignments of the construct. You can implement these outputs with Conditional ("If-Else"), Case, and For Statements.

You can also use Always Constructs with Event Control to create sequential logic. See Implementing Sequential Logic for more information.

The example below shows an Always Construct that counts the number of '1' bits in the input array d. The input d is the only variable in the Event Control of the Always Construct, i.e., the only variable that will cause a change in one or more Procedural Assignment(s) in the construct.

module proc (d, q);

input  [2:0] d;
output [1:0] q;

integer num_bits;

always @ (d)
begin: block
   integer i;

    num_bits = 0;
    for (i = 0; i < 3; i = i + 1)
       if (d[i] == 1)
            num_bits = num_bits + 1;
end

assign q = num_bits;

endmodule

In the example above, d is declared as an input array to the module. Every time d changes, the Procedural Assignments in the Always Construct execute. When data passes through the For Statement and i is less than 3, i is set to the next value, and d(i) accesses information from the d array. If d(i) equals 1, the Conditional ("If-Else") Statement increments num_bits. If d(i) never equals 1 during the execution of the For Statement, num_bits remains at 0. The num_bits integer is then assigned to the output array q, which is also declared in the module.

For more information, see the following sections of the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual:

• Section 6.1: Continuous Assignments
• Section 9.2: Procedural Assignments
• Section 9.4: Conditional Statements
• Section 9.5: Case Statements
• Section 9.6: Looping Statements
• Section 9.7.2: Event Control
• Section 9.9.2: Always Constructs

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