|
Selected Signal Assignment Statements list alternatives that are available for each value of an expression, then select a course of action based on the value of the expression.
You can use Selected Signal Assignments to create multiplexers, as shown below.
ENTITY selsig IS PORT ( d0, d1, d2, d3 : IN STD_LOGIC; s : IN INTEGER RANGE 0 TO 3; output : OUT STD_LOGIC ); END selsig; ARCHITECTURE maxpld OF selsig IS BEGIN WITH s SELECT -- creates a 4-to-1 multiplexer output <= d0 WHEN 0, d1 WHEN 1, d2 WHEN 2, d3 WHEN 3; END maxpld;
The select expression, which is located between the WITH
and SELECT
keywords, selects the
signal that is to be assigned to the target signal. In this example, when the value of the s
multiplexer select expression is 0
, the multiplexer output d0
is assigned to the target signal
output
. When the value of s
is 1
, the output is d1
; when s
is 2
, the output is d2
; when s
is 3
,
the output is d3
.
The select signal can also be declared as an enumeration type, as shown below:
PACKAGE meals_pkg IS TYPE MEAL IS (BREAKFAST, LUNCH, DINNER, MIDNIGHT_SNACK); END meals_pkg; USE work.meals_pkg.all; ENTITY selsigen IS PORT ( previous_meal : IN MEAL; next_meal : OUT MEAL ); END selsigen; ARCHITECTURE maxpld OF selsigen IS BEGIN WITH previous_meal SELECT next_meal <= BREAKFAST WHEN DINNER | MIDNIGHT_SNACK, LUNCH WHEN BREAKFAST, DINNER WHEN LUNCH; END maxpld;
When the value of the previous_meal
multiplexer select signal is equal to the constant DINNER
or MIDNIGHT_SNACK
, the multiplexer output is BREAKFAST
. When previous_meal
is
BREAKFAST
, the output is LUNCH
. When previous_meal
is LUNCH
, the output is DINNER
.
For more information, see "Section 9.5: Concurrent Signal Assignment Statements" in the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual.
- PLDWorld - |
|
Created by chm2web html help conversion utility. |