VHDL

Using Concurrent Signal Assignment Statements



Concurrent Signal Assignment Statements assign values to signals, directing the Compiler to create simple gates and logical connections. Refer to the following topics for more information about the different types of Concurrent Signal Assignment Statements:

For more information, see "Section 9.5: Concurrent Signal Assignment Statements" in the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual.


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