Verilog HDL Templates
Templates for the following Verilog HDL constructs are available for use in Verilog Design Files (.v):
- Always Construct
- Case Statement
- Casex Statement
- Casez Statement
- Conditional Expression
- Continuous Assignment
- For Statement
- Full Design: Counter
- Function Declaration
- If Statement
- Integer Declaration
- Logic Function (and)
- Logic Function (buf)
- Logic Function (nand)
- Logic Function (nor)
- Logic Function (not)
- Logic Function (or)
- Logic Function (xnor)
- Logic Function (xor)
- Module Declaration
- Module Instantiation
- Overall Structure
- Parameter Declaration
- Port Declaration
- Register Declaration
- Supply0 Declaration
- Supply1 Declaration
- Task Statement
- Tri Declaration
- Wand Declaration
- While Statement
- Wire Declaration
- Wor Declaration
Back to Top
| Created by chm2web html help conversion utility. |
