VHDL Templates
Templates for the following VHDL constructs are available for use in VHDL Design Files (.vhd):
- Architecture Body
- Case Statement
- Component Declaration
- Component Instantiation Statement
- Concurrent Procedure Call Statement
- Concurrent Signal Assignment Statement
- Conditional Signal Assignment Statement
- Constant Declaration
- Entity Declaration
- For Statement
- Full Design: Counter
- Full Design: Flipflop
- Full Design: Tri-State Buffer
- For Generate Statement
- If Generate Statement
- If Statement
- Library Clause
- Overall Structure
- Package Declaration
- Procedure Call Statement
- Process Statement (Combinatorial Logic)
- Process Statement(Sequential Logic)
- Selected Signal Assignment
- Signal Assignment Statement
- Signal Declaration
- State Machine with Asynch. Reset
- State Machine without Asynch. Reset
- Subtype Declaration
- Type Declaration
- Use Clause
- Variable Assignment Statement
- Variable Declaration
- Wait Statement
- While Statement
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