See Also

If you do not specify timing requirement settings and/or options, the Quartus^® II Timing Analyzer will run the analyses using default settings. By default, the Timing Analyzer calculates and reports the f_MAX of every register, the worst-case register-to-register delays, the t_SU and t_H of every input register, the t_CO of every output register, and the t_PD between all pin-to-pin paths in the current compilation focus design entity.