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Displays a list of modules or hierarchy of modules and submodules representing stages of a compilation, analysis, analysis and elaboration, or simulation.
Modules Displayed During Compilation, Analysis, Analysis and Elaboration, or Analysis and Synthesis
| Processing Total | The total of all processes carried out for the compilation. |
| Initialization | The stage prior to compilation in which the Compiler creates the database. |
| Compiler Total | The total of the modules or stages of a compilation. |
| Database Builder | The Compiler module that builds a single project database that integrates all the design files in a project hierarchy. As a first step, the Database Builder analyzes all the design files in the project or design entity for syntax and semantic errors. You can choose Start > Start Analysis & Elaboration (Processing menu), rather than Start Compilation (Processing menu), to halt the Compiler when the initialization and the analysis and elaboration processes are completed. This module also performs "high-level synthesis." For example, it infers flipflops, latches and state machines from "behavioral" languages, such as Verilog HDL and VHDL. In addition, it replaces operators, such as + or -, with modules from the Altera® library of implemented parameterized modules (also called "parameterized functions") from LPM version 2.1.0, which offer architecture-independent design entry for Quartus® II-supported devices. |
| Logic Synthesizer | The Compiler module that synthesizes and performs technology mapping on the logic in the project's design files. You can choose Start > Start Analysis & Synthesis (Processing menu), rather than Start Compilation (Processing menu), to halt the Compiler when the synthesis and technology mapping are completed. This module is not displayed during analysis or analysis and elaboration. |
| Fitter | The Compiler module that fits the logic of a project into one or more devices. This module is not displayed during analysis, analysis and elaboration, or analysis and synthesis. |
| Design Assistant | The Design Assistant module checks the reliability of the design based on a set of design rules. This module is not displayed during analysis, analysis and elaboration, or analysis and synthesis. |
| Assembler | The Compiler module that creates one or more programming files for programming or configuring the device(s) for a project. This module is not displayed during analysis, analysis and elaboration, or analysis and synthesis. |
| Timing Analyzer |
The Compiler module that also includes the Delay Annotator, computes delays for the given design and device and annotates them on the netlist for subsequent use by the Simulator or the Timing Analyzer. The Timing Analyzer module analyzes the performance of a project after the Delay Annotator computes and annotates the project's delays. This module is not displayed during analysis, analysis and elaboration, or analysis and synthesis. |
| Netlist |
The Netlist Writer module generates output netlist files for use with other EDA tools. This module is not displayed during analysis, analysis and elaboration, or analysis and synthesis. |
Modules Displayed During Simulation
| Processing Total | The total of all processes carried out for the simulation. If you perform a timing or functional simulation without first compiling the design entity or project, the Processing Total also includes the Compiler Total. |
| Initialization | The stage prior to simulation in which the Simulator creates the database. |
| Simulator Total | The sum of the modules or stages of the simulation. |
| Netlist Writer | The Simulator module that builds the simulation netlist out of a given compiler settings result. As a first step, the Netlist Builder extracts the simulation netlist. In functional simulation, the simulation netlist is composed of flattened netlists extracted from the design files. In timing simulation, the simulation netlist is extracted from the Compiler database netlist, which includes estimated or actual timing information. You can choose Initialize Simulation (Processing menu), rather than Run Simulation (Processing menu) to halt the Simulator when the initialization and the extraction processes are completed. |
| Simulator | The Simulator module that uses the Vector Waveform File (.vwf) (if any) or a Tcl test bench to simulate the design. |
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- PLDWorld - |
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