A Tcl Script File (.tcl) that describes the input vectors that drive simulation. In a Tcl test bench, you can use the same Tcl commands--including Quartus^® II Application Programming Interface (API) functions used as commands--that you can in any other Tcl Script File.

A Tcl test bench specifies the following:

• The input logic levels (that is, vectors) that drive the input pins and determine the internal logic levels throughout the project.

• The nodes to be observed, saved to a file, compared to another node, or manipulated in any other manner allowed by Tcl commands.

Nine-level project inputs without vectors are automatically assigned uninitialized (U) logic levels during simulation. Expected output levels are optional in a Tcl test bench.

You can use the Quartus II Text Editor to create and edit the Tcl test bench. You can run the Tcl test bench in command-line mode or in the Quartus II Tcl Console window.

The following Tcl script represents a Tcl test bench:

project open chiptrip
project set_active_sim chiptrip
sim initialize
while { ![sim is_initialized] } {
  if { ![is_command_line_mode] } {
    set x 0
    after 1000 { set x 1}
    vwait x
  }
  FlushEventQueue
}

sim print info "Simulation is initialized"  									 

					  									 
sim testbench_mode true                   									 

sim force_value {dir\[0\]} 0              									 
sim force_value {dir\[1\]} 1              									 
sim force_value clock 0                   									 
sim run 10ns                              									 
sim get_value at_altera					  									 
sim force_value reset 1                   									 
sim testbench_mode false                  									 
sim run end                               									 
while { [sim is_running] } {
  if { ![is_command_line_mode] } {
    set x 0
    after 1000 { set x 1}
    vwait x
  }
  FlushEventQueue
}

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