Primitive

TFF Primitive



AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION TFF (T, CLK, CLRN, PRN)
   RETURNS (Q);


VHDL Component Declaration:

COMPONENT TFF
   PORT (t   : IN STD_LOGIC;
      clk : IN STD_LOGIC;
      clrn: IN STD_LOGIC;
      prn : IN STD_LOGIC;
      q   : OUT STD_LOGIC);
END COMPONENT;
Inputs
PRN CLRN CLK T
Output
Q
L H X X
H L X X
L L X X
H H L
H H H
H H L X
H
L
Illegal
Qo*
Toggle
Qo*

* Qo = level of Q before clock pulse

All flipflops are positive-edge-triggered.


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