TFF Primitive
AHDL Function Prototype (port name and order also apply to Verilog HDL):
FUNCTION TFF (T
, CLK
, CLRN
, PRN
)
RETURNS (Q
);
VHDL Component Declaration:
COMPONENT TFF
PORT (t : IN STD_LOGIC;
clk : IN STD_LOGIC;
clrn: IN STD_LOGIC;
prn : IN STD_LOGIC;
q : OUT STD_LOGIC);
END COMPONENT;
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Qo* |
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* Qo = level of Q before clock pulse
All flipflops are positive-edge-triggered.
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