Primitive

SRFFE Primitive



AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION SRFFE (S, R, CLK, CLRN, PRN, ENA)
   RETURNS (Q);


VHDL Component Declaration:

COMPONENT SRFFE
   PORT (s   : IN STD_LOGIC;
      r   : IN STD_LOGIC;
      clk : IN STD_LOGIC;
      clrn: IN STD_LOGIC;
      prn : IN STD_LOGIC;
      ena : IN STD_LOGIC;
      q   : OUT STD_LOGIC);
END COMPONENT;
Inputs
ENA PRN CLRN CLK S R
Output
Q
X L H X X X
X H L X X X
X L L X X X
X H H L X X
X H H L L
X H H H L
X H H L H
X H H H H
L H H X X X
H
L
Illegal
Qo*
Qo*
H
L
Toggle
Qo*

* Qo = level of Q before clock pulse

All flipflops are positive-edge-triggered.

NOTE When the ENA (clock enable) input is high, the flipflop passes a signal that is dependent on the S and R inputs to Q. When the ENA input is low, the state of Q is maintained, regardless of the S and R inputs.

For devices that do not support clock enable, logic synthesis generates logic equations containing flipflops with clock enables. These logic equations correctly emulate the logic specified in the project.


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