See Also

FUNCTION LATCH (D, ENA)
   RETURNS (Q);

COMPONENT LATCH
   PORT (d  : IN STD_LOGIC;
      ena: IN STD_LOGIC;
      q  : OUT STD_LOGIC);
END COMPONENT;

* Qo = level of Q before clock pulse

Latches are level-sensitive.

When the ENA (latch enable) input is high, the latch passes a signal from D to Q. When the ENA input is low, the state of Q is maintained, regardless of the D input.

For devices that do not support latch enable, logic synthesis generates logic equations containing latches with latch enables. These logic equations correctly emulate the logic specified in the project.

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