Primitive

JKFF Primitive

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION JKFF (J, K, CLK, CLRN, PRN)
   RETURNS (Q);


VHDL Component Declaration:

 
COMPONENT JKFF
   PORT (j   : IN STD_LOGIC;
      k   : IN STD_LOGIC;
      clk : IN STD_LOGIC;
      clrn: IN STD_LOGIC;
      prn : IN STD_LOGIC;
      q   : OUT STD_LOGIC);
END COMPONENT;
Inputs
PRN CLRN CLK J K
Output
Q
L H X X X
H L X X X
L L X X X
H H L X X
H H L L
H H H L
H H L H
H H H H
H
L
Illegal
Qo*
Qo*
H
L
Toggle

* Qo = level of Q before clock pulse

All flipflops are positive-edge-triggered.


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