Megafunction

lpm_xor (XOR Gate) Megafunction

Parameterized XOR gate. Altera® recommends using the XOR primitive or operator rather than lpm_xor for easier implementation and to improve compilation time. However, lpm_xor may be useful if you need parameterized inputs.

Altera also recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_xor (data[LPM_SIZE-1..0][LPM_WIDTH-1..0])
   WITH (LPM_WIDTH, LPM_SIZE)
   RETURNS (result[LPM_WIDTH-1..0]);

 

VHDL Component Declaration:

 
COMPONENT lpm_xor
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_SIZE: POSITIVE;
      LPM_TYPE: STRING := "LPM_XOR";
      LPM_HINT: STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_2D(LPM_SIZE-1 DOWNTO 0, LPM_WIDTH-1 DOWNTO 0);
      result: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
data[][] Yes Data input to the OR gate. Input port LPM_SIZE x LPM_WIDTH wide. Two-dimensional bus ports are not supported in Verilog HDL.

OUTPUT PORTS

Port Name Required Description Comments
result[] Yes Each result[] bit is the XOR of LPM_SIZE bits. Output port LPM_WIDTH wide.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the data[][] and result[] ports. Number of XOR gates.
LPM_SIZE Integer Yes Number of inputs to each XOR gate. Number of input buses.
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

 

Truth Table/Functionality:

Each lpm_xor function defines LPM_WIDTH XOR gates. Each XOR gate has the following function:

Inputs Outputs
data[LPM_SIZE-1]_[LPM_WIDTH-1] Note (1) result[LPM_WIDTH-1]
Even 0
Odd 1

 

Resource Usage:

Uses one logic cell per output.

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