See Also

Allows you to select an HDL design file type or a schematic.

If you select a schematic, the Quartus^® II software generates an empty Block Design File (.bdf) with pins that represent the I/Os in the block.

If you select an HDL file type, the Quartus II software generates the HDL file, which includes a template for a module declaration, with port declarations that correspond to the data you entered in the block.

You may notice a few pairs of Quartus II–generated comments that start with "ALTERA" and end with "DO NOT REMOVE THIS LINE!" The information between these pairs of comments may be updated automatically, so you must not enter text between them. However, you can enter other Verilog HDL statements outside those commented sections.