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For each I/O in the block, a corresponding I/O is generated in the HDL you select. The parts of the generated HDL code are marked so that they may be updated if the I/Os in the block change, without changing the implementation code in the design file, and if the I/O and the parameter code in the design file are updated, but the other code is unchanged.

After you choose Create Design File from Selected Block (right button pop-up menu) or Create/Update > Create Design File from Selected Block (File menu), the design file, which includes a template for a module declaration with the ports already specified, opens automatically.

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