See Also

The following example shows a sample test bench file that can be used in Example of Performing a Functional Simulation on a Verilog HDL Design with a Custom Megafunction Variation with the ModelSim^® Software. In this example, the test bench file name is cam_wrapper_test.v.

Cam_wrapper_test.v
`timescale 1 ns / 1 ns

module cam_wrapper_test();

wire [31:0] pattern;
reg [4:0] wraddress;
reg wren;
reg [31:0] wrx;
reg wrxused;
reg wrdelete;
reg inclock;
reg inclocken;
reg inaclr;
wire [4:0] maddress;
wire mfound;
wire [4:0] mcount;
wire rdbusy;
wire wrbusy;

reg [31:0] cnt;
reg clock_count;

camsource L0(.pattern(pattern), .wrx(wrx), .wrxused(wrxused), .wrdelete(wrdelete),
.wraddress(wraddress), .wren(wren), .inclock(inclock), .maddress(maddress),
.mfound(mfound), .mcount(mcount), .rdbusy(rdbusy),.wrbusy(wrbusy),
.inclocken(inclocken));

initial
begin
	assign inclocken = 1'b1;
	wrx = 8'b00000000;
	wrxused = 1'b0;
	wrdelete = 1'b0;
	inaclr = 1'b1;
	wren = 1'b0;
initial cnt = 0;
end

assign pattern = cnt;

initial
begin
   	inclock = 1'b0;
   	forever #5 inclock = ~inclock;
end

initial
begin
   	clock_count = 1'b0;
   	forever #50 clock_count = ~clock_count;
end  

always@(posedge clock_count)
begin
	cnt = cnt + 1;
end

endmodule

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