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When you turn on Generate a compilable netlist automatically from the source files when they change, the Quartus^® II software generates a script that runs the specified tool with the default settings from within the Quartus II software. When the source files change, the specified tool automatically generates a gate-level netlist file for use with the Quartus II software.

The following figure shows a sample script that may be generated from the Quartus II software through this option:

Figure 1. Sample Script from Generating a Compilable Netlist Automatically

/* Altera® generated script */
search_path = { F:/QUARTUS/eda/synopsys/fc/syn/apex20k/lib } +  search_path;
link_library = apex20k-3_fpga.db;
target_library = apex20k-3_fpga.db;
synthetic_library = apex20k-3_fpga.sldb;
define_design_lib DW_APEX20K-3_FPGA  -path F:/QUARTUS/eda/synopsys/dw/lib;
cd ..;
read -format verilog prep2.v;
cd dc_work;
include  ../prep2_constraints.scr;
current_design prep2;
uniquify;
compile;
replace_fpga -force;
write -f verilog -hierarchy prep2 -output prep2_syn.v;
quit;

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