See Also

The following sample shows the lvds_rx_1wrapper.v file, which can be generated by the MegaWizard^® Plug-In Manager, as described in Example of Creating a Verilog HDL Custom Variation of the altlvds_rx Function.

// megafunction wizard: %ALTLVDS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altlvds_rx 

// ============================================================
// File Name: lvds_rx_wrapper.v
// Megafunction Name(s):
// 			altlvds_rx
// ============================================================
// ************************************************************
// THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************


module lvds_rx_wrapper (
	rx_in,
	rx_inclock,
	rx_deskew,
	rx_out,
	rx_outclock);

	input	[1:0]  rx_in;
	input	  rx_inclock;
	input	  rx_deskew;
	output	[7:0]  rx_out;
	output	  rx_outclock;

	wire [7:0] sub_wire0;
	wire  sub_wire1;
	wire [7:0] rx_out = sub_wire0[7:0];
	wire  rx_outclock = sub_wire1;

	altlvds_rx	altlvds_rx_component (
				.rx_deskew (rx_deskew),
				.rx_inclock (rx_inclock),
				.rx_in (rx_in),
				.rx_out (sub_wire0),
				.rx_outclock (sub_wire1));
	defparam
		altlvds_rx_component.intended_device_family = "APEX™20KE",
		altlvds_rx_component.number_of_channels = 2,
		altlvds_rx_component.deserialization_factor = 4,
		altlvds_rx_component.inclock_period = 1,
		altlvds_rx_component.registered_output = "ON";


endmodule

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