Example of a Verilog HDL Custom Megafunction Variation of altcam
The following sample shows the cam_wrapper_v.v file, which can be generated by the MegaWizard® Plug-In Manager as described in Example of Creating a Verilog HDL Custom Variation of the altcam Function.
// megafunction wizard: %ALTCAM%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTCAM
// ============================================================
// File Name: cam_wrapper_v.v
// Megafunction Name(s):
// ALTCAM
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
module cam_wrapper_v (
pattern,
wraddress,
wren,
wrx,
wrxused,
wrdelete,
inclock,
inclocken,
inaclr,
maddress,
mfound,
mcount);
input [31:0] pattern;
input [4:0] wraddress;
input wren;
input [31:0] wrx;
input wrxused;
input wrdelete;
input inclock;
input inclocken;
input inaclr;
output [4:0] maddress;
output mfound;
output [4:0] mcount;
wire [4:0] sub_wire0;
wire [4:0] sub_wire1;
wire sub_wire2;
wire [4:0] mcount = sub_wire0[4:0];
wire [4:0] maddress = sub_wire1[4:0];
wire mfound = sub_wire2;
altcam altcam_component (
.wrxused (wrxused),
.inclocken (inclocken),
.wren (wren),
.inclock (inclock),
.wrx (wrx),
.pattern (pattern),
.inaclr (inaclr),
.wraddress (wraddress),
.wrdelete (wrdelete),
.mcount (sub_wire0),
.maddress (sub_wire1),
.mfound (sub_wire2));
defparam
altcam_component.width = 32,
altcam_component.widthad = 5,
altcam_component.numwords = 32,
altcam_component.match_mode = >SINGLE>,
altcam_component.pattern_reg = >INCLOCK>,
altcam_component.wrx_reg = >INCLOCK>,
altcam_component.wrx_aclr = >ON>,
altcam_component.pattern_aclr = >ON>,
altcam_component.wrcontrol_aclr = >ON>,
altcam_component.wraddress_aclr = >ON>,
altcam_component.output_aclr = >ON>,
altcam_component.lpm_file = >my_cam.hex>,
altcam_component.lpm_filex = >my_cam_xu.hex>;
endmodule
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