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The EPM3032A, a member of the MAX® 3000 family, is based on second-generation MAX architecture and provides 32 registers and 600 usable gates. The EPM3032A meets the low power and voltage requirements of 3.3-V applications ranging from notebook computers to battery-operated, hand-held equipment.
EPM3032A devices are available in 44-pin PLCC packages with 30 I/O pins and 44-pin TQFP packages with 30 I/O pins. Each device also contains four dedicated inputs.
The EPM3032 has 32 macrocells divided into 2 LABs. Each macrocell consists of a logic array, a product–term select matrix, and a programmable register. Each macrocell in a LAB can be supplemented with up to 16 shareable expander product terms and 15 high–speed parallel expander product terms to provide up to 32 product terms per macrocell for building complex logic functions. The EPM3032A also supports in-system programmability (ISP) and JTAG BST. The EPM3032A JTAG Instruction Register length is 10; the Boundary-Scan Register length is 96; and the JTAG ID code is 170320DD.
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Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EPM3032A device, refer to the current MAX 3000A Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site. |
The following table displays the pin-out information for EPM3032A devices:
Function Config. LCell OE MUX LAB IO PLCC TQFP
Pin Pin;LCell Bank 44 44
Note (10)
Input/GCLK - - -/- - - 43 37
Input/OE1n - - 1/- - - 44 38
Input/GCLRn - - -/- - - 1 39
Input/OE2n/GCLK - - 2/- - - 2 40
I/O or Buried - 1 -/3 A - 4 42
I/O or Buried - 2 1/- A - 5 43
I/O or Buried - 3 -/- A - 6 44
I/O or Buried TDI 4 -/- A - 7 1
I/O or Buried - 5 -/- A - 8 2
I/O or Buried - 6 -/4 A - 9 3
I/O or Buried - 7 6/- A - 11 5
I/O or Buried - 8 -/5 A - 12 6
I/O or Buried TMS 9 -/- A - 13 7
I/O or Buried - 10 -/1 A - 14 8
I/O or Buried - 11 2/- A - 16 10
I/O or Buried - 12 3/- A - - -
I/O or Buried - 13 5/- A - 18 12
I/O or Buried - 14 -/6 A - 19 13
I/O or Buried - 15 4/- A - 20 14
I/O or Buried - 16 -/- A - 21 15
I/O or Buried - 17 -/3 B - 41 35
I/O or Buried - 18 1/- B - 40 34
I/O or Buried - 19 -/2 B - 39 33
I/O or Buried TDO 20 -/- B - 38 32
I/O or Buried - 21 -/- B - 37 31
Function Config. LCell OE MUX LAB IO PLCC TQFP
Pin Pin;LCell Bank 44 44
Note (10)
I/O or Buried - 22 -/4 B - - -
I/O or Buried - 23 6/- B - 34 28
I/O or Buried - 24 -/5 B - 33 27
I/O or Buried TCK 25 -/- B - 32 26
I/O or Buried - 26 -/- B - 31 25
I/O or Buried - 27 2/- B - 29 23
I/O or Buried - 28 3/- B - 28 22
I/O or Buried - 29 5/- B - 27 21
I/O or Buried - 30 -/6 B - 26 20
I/O or Buried - 31 4/- B - 25 19
I/O or Buried - 32 -/- B - 24 18
VCCINT - - - - - 3 17
VCCINT - - - - - 23 41
VCCIO - - - - - 15 9
VCCIO - - - - - 35 29
GND - - - - - 10 4
GND - - - - - 17 11
GND - - - - - 22 16
GND - - - - - 30 24
GND - - - - - 36 30
GND - - - - - 42 36
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