See Also

Specifies where on the current EPXA1 device you want to route the input signals, output signals, and other signals (such as address and control signals) for EPXA1 dual-port RAM in the following modes:

• For EPXA1 dual-port RAM that is in 8-bit or 16-bit single-port mode, select routing paths for the dual-port RAM signals using the following options:

  Input signals	Routes the input data to either MegaLAB™ column 1 or 2.
  Output signals	Routes the output data to either MegaLAB column 1 or 2.
  Other signals	Routes the data of other signals, such as address and control signals, to either MegaLAB column 1 or 2.

• For EPXA1 dual-port RAM that is in 32-bit single-port mode, select routing paths for the dual-port RAM signals using the following options:

  Input signals	Routes the input data to either MegaLAB column 1 or 2. When the input data is routed to a MegaLAB column, the three MSB bits of the dual-port RAM's PLD-To-Stripe Bridge are routed to the other MegaLAB column. For example, when the input data is routed to MegaLAB column 1, the three MSB bits of the dual-port RAM's PLD-To-Stripe Bridge are routed to MegaLAB column 2.
  Output signals	Individually routes the lower 32 bits and upper 32 bits of output data to MegaLAB column 1 or 2. The setting Lower to 1, Upper to 1ESB routes the lower 32 bits of the output data to the section of MegaLAB column 1 that is not adjacent to the Embedded System Block (ESB), and routes the upper 32 bits of the output data to the section of MegaLAB column 1 that is adjacent to the ESB.
  Other signals	Routes the data of other signals, such as address and control signals, to either MegaLAB column 1 or 2.

• For EPXA1 dual-port RAM that is in dual-port or two single-port mode, select routing paths for the dual-port RAM signals using the following options:

  Select Dual Port in the Existing dual-port RAM routing settings list to select routing paths for dual-port RAM that is in either dual-port or two single-port mode.

  Input signals	Routes the input data of each dual-port or two single-port mode dual-port RAM to MegaLAB column 1 or 2. When the input data is routed to a MegaLAB column, the three MSB bits of the PLD-To-Stripe Bridge are routed to the other MegaLAB column. For example, when the input data is routed to MegaLAB column 1, the three MSB bits of the PLD-To-Stripe Bridge are routed to MegaLAB column 2. The setting DPRAM0 to 2, DPRAM1 to 2ESB routes the input data of DPRAM0 to the section of MegaLAB column 2 that is not adjacent to the ESB, and routes the input data of DPRAM1 to the section of MegaLAB column 2 that is adjacent to the ESB.
  Output signals	Routes the output data of each dual-port or two single-port mode dual-port RAM to MegaLAB column 1 or 2. The setting DPRAM0 to 1, DPRAM1 to 1ESB routes the output data of DPRAM0 to the section of MegaLAB column 1 that is not adjacent to the ESB, and routes the output data of DPRAM1 to the section of MegaLAB column 1 that is adjacent to the ESB.
  Other signals	Routes the data of other signals, such as address and control signals, in DPRAM0 to MegaLAB column 1, and the data of other signals in DPRAM1 to MegaLAB column 2.

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