CoreABC is a powerful and easy-to-use solution for a broad range of embedded control applications. It is also the industry's smallest and first RTL-programmable soft micro for FPGAs.
CoreABC features deterministic operation, very fast I/O response (less than 100 nanoseconds) and supports the advanced peripheral bus (APB) interface. Since CoreABC can be implemented in as few as 241 tiles, it can be used in small Actel devices, such as the flash-based A3P030 ProASIC3 device. Implementation for CoreABC starts at less than 10 cents per instantiation.
CoreABC can be used on the following Actel devices:
- Fusion
- ProASIC3/E
- ProASICPLUS
- Axcelerator
- RTAX-S
CoreABC is delivered through CoreConsole and includes:
- Free obfuscated version
- RTL version available for $5,000
- Test benches — VHDL & Verilog
- Core documentation
CoreABC can be programmed in either hardware or software. The instructions executed are either held in a small internal ROM constructed from logic tiles (hardware programmed), or stored in RAM blocks internal to CoreABC (software programmed).
The RAM blocks can be initialized using the embedded flash memory within the Fusion family or another external source (e.g., CoreMP7).
CoreABC stands for APB Bus Controller.
- Instruction Block Contains instruction
counter and instruction table and instruction to be
executed - ALU and Flags Each supported ALU operation can be disabled to reduce size
- Storage Provides local storage for data values and the call stack
- ACM Lookup Small lookup table that holds CoreAI initialization data
- Sequencer Controls operation of the core and handles interrupts
- APB Controller Implements the APB bus protocol and data input MUX
