Processor Co-Verification Solution for ARM7

Worry that a soft processor will give you different results than an off-the-shelf processor? Even though you have to build a support system around the off-the-shelf version to get all the peripherals you need? Putting the processor and all supporting logic in a single chip is more efficient, the question is how do you prove it works on the board?

CoVer™ is a Windows®-based hardware/software co-verification solution, offered by Aldec. It is targeted for Actel's CoreMP7, soft IP ARM7 core, allowing debug of both hardware and software aspects of designs targeted for CoreMP7 in Actel devices. CoVer provides control and visibility across engineering teams, which translates into shorter design schedules and lower project costs.

Utilizing Aldec's patented Smart Clock technology to enable fastest hardware verification and on-demand debugging, the CoVer technology is based on using two clock sources: an HDL simulator generated clock (sw clk) and a hardware oscillator generated clock (hw clk). The programmable Smart Clock unit constantly monitors the AHB Bus to identify bus transactions to Custom Peripherals simulated in HDL. Whenever the transaction to the programmed address range is detected, the system clock is switched to the HDL simulator, allowing for debugging of the AHB bus and peripherals. Once the transaction is completed, the clock is switched back Processor Co-Verification Solution for ARM7 to the hardware oscillator enabling processor debugging with a speed of prototyping solutions. The CoVer solution integrates the Active-HDL simulator with the board. The CoreMP7 processor memory and standard peripherals reside in Actel's ARM-enabled M7A3P1000 ProASIC3 FPGA on the board. Aldec's patented sw/hw interfacing allows for the simulation and debugging in Active-HDL waveform viewer. The board is connected to the workstation through 32/64-bit to 33/66 MHz PCI slot, providing ease-of-use and high performance.

Reprogrammable through PCI or JTAG, the reusable CoVer board can be used for any CoreMP7-based embedded design.

The Active-HDL suite is a comprehensive and totally integrated environment for digital IC design and verification that employs hardware description languages and C/C++ solutions.

It provides engineers and design teams with tools for efficient and vendor independent design implementation and testing. Of course we prefer that you use Actel.

Active-HDL is tailored to support designers working with FPGA families from different vendors. As a part of the suite, pre-compiled Verilog and VDHL

libraries of all FPGA silicon vendors are delivered in a ready-to-use form.

Active-HDL supports even the most complex FPGA and ASIC designs by providing the following key features: