|
| http://www.vim.org |
Verilog : Jeff Solomon maintains his page on vim syntax files for Verilog along with C, perl, csh, Tcl at http://www-flash.stanford.edu/~jsolomon/vim/
Vera: Beth Leonard of Hewlett-Packard posted this vim syntax file for vera in ESNUG.
Design Compiler: Gzim Derti posted this vim syntax file file for synthesis in ESNUG.
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many verilog files. It parses verilog code into a database that can be used to navigate files, trace connectivity, and find modules and signals in the design. It can even parse your files as you edit so you don't launch those long compile scripts only to end up with a syntax error after 5 minutes of compiling.
New features include a new Verilog menu with configurable links to Verilog lint, compile, simulate, and debug commands, and the latest version of Source Navigator 5.1.1 Downloads are available for Solaris and Linux.
http://snverilog.sourceforge.net/
TimingTool is a free to use on-line Timing
Diagram Editor. This tool provides very good VHDL and Verilog test benches
and requires no download or installation.
http://www.timingtool.com
A more advanced application version of this tool including an HDL editor is
available from Saros and is called TurboWriterPro. This can be downloaded
for evaluation from:
http://www.saros.com/turbowriter
Revision
Control Software
CVS is widely used revision control software.
The Concurrent Versions System (CVS) provides network-transparent source
control for groups of developers.
Features:
- maintains a history of all changes made to each directory tree it manages
- provides hooks to support process control and change control
- provides reliable access to its directory trees from remote hosts using Internet protocols
- supports parallel development allowing more than one developer to work on the same sources at the same time
An excellent documentation is available at http://www.gnu.org/manual/cvs-1.9/cvs.html
InnerLoop ( http://www.posedgesoft.com/products.shtml )
InnerLoop™ is an Open Development Environment for Verilog, VHDL, SystemC, and other C/C++ applications for hardware design engineers, verification engineers, and EDA developers.
Synthesizable
Arithmetic Module Generator
Generate synthesizable adders, subtractor,
multiplier, squarer with this fully configurable web based tool. http://modgen.fysel.ntnu.no/~pihl/iwlas98/
It is developed by Johnny Pihl - Espen Sand of Norwegian University of Science and Technology. More information of this project is available at http://modgen.fysel.ntnu.no/~pihl/iwlas98/
Synthesizable
CRC functions
Generate synthesizable CRC functions with
web based tool from Easics http://www.easics.com/webtools/crctool
More theoretical information on crc is
available at
ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
vpp:
A Powerful Verilog Preprocessor
Hemi Thaker wrote this utility to emulate
VHDL's "generate" statement.
For example the code fragment shown on
left side will get converted into code fragment shown on right side after
passing through vpp Verilog preprocessor.
It is available at http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=tr007
| `for (i=0; i<4; i++)
`let j=i*2; addr addr::`i ( .a (a[`j]) ); `endfor |
addr addr0 (
.a (a[0]) ); addr addr1 ( .a (a[2]) ); addr addr2 ( .a (a[4]) ); addr addr3 ( .a (a[6]) ); |
OpenCores ( http://www.opencores.org/
)
This site is created to to coordinates efforts of creating open source IP cores.
Lots of good cores are available on this site including microprocessor,
arithmetic, communication cores.
HDLMaker (
http://www.polybus.com/hdlmaker/users_guide/ )
HDLmaker is a tool for generating Verilog designs. HDLmaker simplifies the
development of complex FPGA designs as well as PC Boards by performing the
following tasks:
- Writes hierarchical Verilog code
- Generates retargetable IO pad rings
- Generates all of the necessary scripts and Make files
- Supports mulitlanguage projects
- Converts PCB net lists into VHDL and Verilog
- Generates SCALD and PADS PCB board netlists
- Generates Schematics in Postscript format
- Designs are portable between FPGA families and CAE tools
- Simplifies the reuse of HDL code
- Converts HDLmaker, Verilog and VHDL
files into fully hyper linked HTML
The designer writes the leaf cells and defines the pins, HDLmaker does the rest.
HDLmaker generates Verilog and VHDL code, scripts and project files for
FPGAs and ASICs. It supports Synplify, Precision and XST as well as most
common Verilog simulators like NCverilog, VCS and Modelsim. It's
free/open source and licensed under a BSD style license.
Jeda
(Juniper EDA ? :) ( http://www.jeda.org/
)
Atsushi Kasuya of Juniper Networks Inc. developed Jeda. It is a C-like programming language for hardware design verification. It has Verilog-like multi-value bit vector data type and concurrent programming features with the garbage collection support. It also provides object oriented programming support.
Jeda links to Verilog as a user PLI code and runs with Verilog.
The Open Verification Library
(OVL)
Harry Foster who wrote "Principles
of Verifiable RTL Design" started this OVL
website to spread the use of assertion monitor. These initial assertion
monitors specifications are donated by Verplex to OVL.
OpenVera ( http://www.open-vera.com/
)
OpenVera 2.0 combines the strengths of the OpenVera hardware verification language
from Synopsys with Intel’s newest formal verification language (ForSpec) to deliver a more comprehensive, open source hardware verification language to the verification community.
Testbuilder ( http://www.testbuilder.net/
)
TestBuilder provides a C++ signal class, interfacing C++ to an HDL design at the signal level. TestBuilder supports abstraction of tests to the transaction level. It provides concurrency (threading), including dynamic generation of and synchronization between concurrent tasks.
TestBuilder supports both Verilog and VHDL.
Cadence developed Testbuilder but could not make a dent in market as they were late in the game. Making it free / open source may entice many engineers to try and build a user base.
logscan
: A Configurable Error Management Utility
David C. Black, Qualis Design wrote this
perl script to extract exact "information" from huge reports generated
by tools like Synopsys Design Compiler etc. This fully configurable script
extracts information you need from thousands of errors and warning messages
the tools generate. It is available at http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=tr012
ScriptSim : Bring the power of Perl/Tk and Python/Tk to your Verilog?simulations
ScriptSim integrates perl and python including Tk with your verilog simulation. ScriptSim interfaces to any Verilog PLI compliant simulator and dynamically creates perl and/or python processes running your model or verification scripts. With the Perl/Tk or Python/Tk interfaces, your scripts can create professional user interfaces with multiple windows, graphics, and mouse interaction, or you can use the built-in Tk display created automatically by
ScriptSim.
http://www.nelsim.com/
Perl-interface
to speed up verification times with SimWave by Utku
Ozcan.
This program generates compact $shm_probe
task as a Verilog output which can be included in this testbench file.
Detailed description and perl code is available here.
Covered is a Verilog code coverage analysis tool
that can be useful for determining how well a diagnostic test suite is covering
the design under test. A preliminary version is available at
http://covered.sourceforge.net/
This page has a good collection of VCD scripts to fix some problems in VCD creation and comparing two VCDs.
http://www.reptechnic.com.au/vcd.html
Synopsys
Plus Perl (SPP)
SPP is a Perl module that wraps around
Synopsys' shell programs developed by Jeff
Solomon. SPP is inspired by the original dc_perl written by Steve Golson,
but it's an entirely new implementation. Why is it called SPP and not dc_perl?
Well, SPP was written to wrap around any of Synopsys' shells. This
includes:
bc_shell
budget_shell
dc_shell
dp_shell
dt_shell
fpga_shell
lc_shell
pt_shell
ra_shell
However, that's not really the whole story. SPP is a Perl module, not an application. It can be used to fully embed a Synopsys script inside of Perl. SPP was written in an object-oriented way so that each object totally encloses a Synopsys shell process.
The first example of an application using SPP is called synopsys_fe, a frontend replacement for any of the Synopsys shells listed above. synopsys_fe sports a snazzy GNU Readline interface with all of your favorite terminal capabilities (command completion, up/down history, etc), a convenient Perl interface, and other Perl niceties that you might expect.
But wait, there's more! Invoking the Synopsys shell in Tcl mode (SPP supports both Tcl and default Dcsh mode), enables an auxiliary module, Synopsys::Collection. This module maps the functionality provided by Synopsys' collection idiom into Perl.
Sound interesting? Click on http://www-vlsi.stanford.edu/~jsolomon/SPP
SPP is free software. Anyone can redistribute
it and/or modify it under the same terms as Perl itself. Feel free to contact
Jeff (jsolomon@stanford.edu) with any questions, comments, criticisms you
have.
IPOfix
- A Freeware IPO Buffer Resizing Program
Jeff Winston of Maker Communications wrote
this C program to read in Synopsys Primetime ® timing reports
and upsizes gates whose individual delays exceed user-specified limits.
A detailed information is available at http://www.deepchip.com/items/0339-01.asp
and source code is available for download here.
ScriptEDA:
Link scripting languages such as Perl and Tcl to any freely available EDA
tools
This page is dedicated to linking scripting languages such as Perl,Python and Tcl to any freely available EDA tools.
Basic idea is to make friendly interfaces for any existing EDA engines