A mandatory step in digital design process is the analysis, determination and elimination of possible timing violations within any design’s tolerance range.

This fact is becoming more important for nano scale technology and the high speed requirements where greater density of today’s MCM, SOC, NoC and ASIC designs that are pushing the limits of speed.

Any design must consider the fact that component timing varies from component to component chip to chip and board to board.

Each chip/board that is manufactured contains a slightly different combination of fast and slow components that can cause some timing margin.

The ASIC designer must always account for these variations and check timing violation if any within the ASIC chip and in the board that contains the ASIC using worse case corner analysis.

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