Xilinx CPLD에서 Flip-Flop의 초기상태 값을 설정하는 방법은...?

Family: Hardware Product Line: CPLD Part: 9500XL & CoolRunner Family Version:

Record Number: 3123 Created: 10/02/00 17:41:06 Last Modified: 03/05/04 21:47:23 Status: Active

Problem Description:

Keywords: initial, init, CPLD, 9500, CoolRunner, power up, state, XPLA3, preload

Urgency: Standard

General Description: I want the power-up state of a flip-flop to be a logic high ("1"). What type of flip-flop should I use to achieve this? Is there a property that I can attach to a flip-flop so it powers up into a "1" state?

Solution 1:

When the default software settings are used, flip-flops are initialized with a "0". However, when you add the attribute "INIT=S", any flip-flop with this attribute powers up in the "1" state.

For example, with a flip-flop instance named "TEST", place the following in your UCF:

INST TEST INIT=S;

There is a global setting in the software that enables you to set all registers to initialize to a "1", "0", or "FPGA Equivalent". The first two settings are self-explanatory. "FPGA Equivalent" means that if there is a register in your design that is using a Preload signal but no Clear signal, this register will initialize itself with a "1" on power up.

This setting is called "Default Power-up Value of Registers" and is located under the Basic tab in the "Implement Design" preferences.

Solution 2:

In your ABEL code, you can add the following:

xilinx property 'init=s reg_name' ;

Also, add one of the following (depending on whether the register is a node or drives an output pin):

reg_name PIN istype 'reg_name default_1'; // or default_0
reg_name NODE istype 'reg_name default_1'; // or default_0

NOTE: The second line is necessary to ensure proper register initialization for functional simulation.

Solution 3:

You can verify the register initial states by looking at the Fitter report (design.rpt):

ISE Version 6.x, 5.x
Look for the section labeled: "Resources Used by Successfully Mapped Logic."
There will be a column for "Reg Init State." Cross reference this column with the signal name (row) to identify the power-up state of each register.

ISE Version 4.x
- All registered equations will have a .PRLD (abbreviation for "Preload") extension.
- If the .PRLD extension equals GND, this means the register will initialize to "0".
- If the .PRLD extension equals VCC, this means the register will initialize to "1".

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