`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    23:46:39 03/17/06
// Design Name:    
// Module Name:    usb_loopback_interface
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module usb_loopback_interface(usb_data, usb_txe, usb_rxf, usb_rd, usb_wr, int_data, 
                        int_addr, int_read, int_write, int_req, int_gnt, 
                        clock, reset);
	 inout [7:0] usb_data;
    input usb_txe;
    input usb_rxf;
    output usb_rd;
    output usb_wr;
    inout [15:0] int_data;
    output [19:0] int_addr;
    output int_read;
    output int_write;
    output int_req;
    input int_gnt;
    input clock;
    input reset;

		  reg [5:0] state;
reg [7:0] data;
reg usb_rd;
reg usb_wr;
//reg usb_data_oe;
//reg operation_rd;
//reg int_req;
//reg int_read;
reg int_write;
//reg out_msb;

//reg [0:4] slow_clock;

assign int_addr = 20'b0;
assign int_data = {data,8'b0};

assign usb_data[7:0] = usb_wr ? data[7:0] : 8'bz	;

/*
always @ (posedge clock or posedge reset)
	if (reset) slow_clock <= 0;
	else slow_clock <= slow_clock + 1;
  */


always @ (posedge /*slow_clock[0]*/clock or posedge reset)
	if (reset)
	begin
		state <= 0;
		data <= 8'd65;
		usb_rd <= 0;
		usb_wr <= 0;
		//usb_data_oe <= 0;
		//int_req <= 0;
		//operation_rd <= 0;
		//int_read <= 0;
		//int_write <= 0;
		//out_msb <= 0;

	end
	else
		case(state)
		'd0: begin
			//int_req <= 0;
			usb_rd <= 0;
			usb_wr <= 0;
			//usb_data_oe <= 0;
			//int_read <= 0;
			//int_write <= 0;
			if(usb_rxf) state <= state + 1;
			//if(data == 8'd91) data <= 8'd65;
		end
		'd1: begin usb_rd <= 1;
			state <= state + 1;
		end
		'd2: state <= state + 1;
		'd3: begin data <= usb_data;
			usb_rd <= 0;
			state <= state + 1;
		end
		

		'd4: if(usb_txe) state <= state + 1;

 		'd5: begin
				int_write <= 1;
				usb_wr <= 1;
				state <= state + 1;
			end
		'd6: state <= state + 1;
		'd7: begin
				int_write <= 0;
				usb_wr <= 0;
				state <= 0;
			end
		
		default: state <= 0;
		endcase

endmodule