Structured ASICs are a new breed of device that provide the performance of today's Standard Cell ASIC while dramatically simplifying the design complexity. Structured ASICs offer designers a set of specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O. By virtue of the predefined structures, the ASIC vendor can design any time-consuming task - such as test, signal integrity, and power grid issues - into the architecture. By taking this approach, ASIC designers can dramatically reduce the total cost of making an ASIC - the number of tools needed is less, the amount of time and engineering effort to design is less, and the NRE charges are substantially reduced. What typically is sacrificed is the maximum performance that can be achieved in a Structured ASIC versus a Standard Cell ASIC. However, by using custom synthesis technology that uniquely targets each Structured ASIC architecture, the performance lost due to the architecture can be regained through the design tools.

Custom Synthesis vs. Traditional Synthesis

For traditional synthesis for ASICs, a standard cell library is created in the .lib format. Synthesis algorithms map to cells from this library and create a logic implementation. By viewing the Structured ASIC architecture as a standard cell ASIC, traditional synthesis is not able to take advantage of the resources or primitives available in the Structured ASIC architecture, thereby providing sub-optimal results.

Custom synthesis is a brand new methodology developed by Synplicity® that targets the Structured ASIC architecture directly by looking at the primitives that make it up. For example, in a given Structured ASIC architecture, one may find that MUX cells are better to use than NAND cells. Custom synthesis uses this kind of information to pick the best possible cells to implement a function, thereby producing better results.

The use of operators, such as adders, multipliers, shift registers, and other datapath, is very common in designs today. Optimization of these operators is critical for good timing results. In Synplicity's custom synthesis, custom module generators are created for all the operators optimized to each Structured ASIC architecture. The module generators are available in fast and small configurations, and are selected automatically by the tool during synthesis based on the timing constraints on the design. Typically, these operators are both faster and smaller than if generic module generators are used.

A feature of some Structured ASICs are that they consist of tiles that are replicated throughout the device. Each tile contains a fixed number of primitive cells, such as registers, muxes, and inverters. Synthesis thus has an additional constraint, it has to meet the ratios of these primitives in the final implementation. Custom synthesis will ensure that ratios between the various types of primitives are met, thereby reducing area significantly.

It's about timing...

The bottom line is that custom synthesis can provide up to 25% better timing QoR for Structured ASICs compared to traditional synthesis. Customer synthesis takes advantage of the underlying architecture of Structured ASICs by providing improved technology mapping, better optimizations, and architecture-tuned module generators.