ASIC-FPGA high wire act
Crista Souza
ebnonline

04/01/2004 9:00 AM EST
URL: http://www.my-esm.com/showArticle.jhtml?articleID=18401678

Remember when ASIC was ASIC and FPGA was an afterthought? It wasn't that long ago--maybe 10 years--but technology and market forces have done a lot to blur the distinction.

Where there had been a clear delineation between the capabilities of field-programmable gate arrays (FPGAs) and application-specific ICs (ASICs), the difference is becoming less obvious. Each still has its strengths and weaknesses, but broad assumptions can no longer be made when considering which approach will satisfy the design requirements and bring the quickest return on investment.

"It's not as clear-cut as it used to be," said Jeff Ittel, president of Avnet Cilicon, the semiconductor group of Phoenix-based distributor Avnet Inc. "There are more and more decisions to be made as FPGAs and ASICs come toward each other."

ASIC in this case refers to structured ASIC, a faster, denser generation of gate array that emerged when suppliers sought to recapture midvolume, mid-density market share lost to increasingly sophisticated field-programmable parts.

Structured ASICs embed certain elements common to most designs, and reserve from one to four metal layers for customization. The advantages over standard-cell ASICs are that mask costs can be as much as 90 percent lower, EDA tools less expensive and design cycles shorter, though the performance is substantially lower.

Average selling prices for structured ASICs are about one-tenth those of FPGAs. The trade-off is that FPGAs are still cheaper on the front end, having no nonrecurring engineering (NRE) costs, and their programmability allows post-fab design changes without re-spinning the silicon.

"If you can get away from using an ASIC, you do," said Paul Terry, chief technology officer of OctigaBay Systems Corp., a venture-capital-backed supercomputer OEM based in Burnaby, British Columbia. "They're almost a last resort nowadays."

The exceptions, according to Terry, are when you must have high volume or performance, which he characterized as a combination of gates and speed. It was the latter--specifically serializer/deserializer (serdes) speed--that led OctigaBay to consider an ASIC for its 12K supercomputer.

The 12K prototype was built using a Virtex II Pro FPGA from Xilinx Inc. (San Jose, Calif.), configured as an internal switch that connects the 12 system CPUs to an extremely fast I/O fabric. Given the performance requirement, OctigaBay looked at structured ASIC alternatives from AMI Semiconductor, LSI Logic and Toshiba, but none of those had serdes interfaces. An Altera FPGA was also considered for the prototype, but OctigaBay found the Xilinx offering to be broader in capability overall, Terry said.

Originally, the FPGA was to be spun into a standard-cell ASIC to reduce system cost and allow more headroom for features that didn't fit in the Xilinx chip. In the end, the company took the FPGA to production.

"We initially thought we wouldn't get everything we needed in the FPGA, but we've been pleasantly surprised. And Xilinx knows they're in competition with semicustom vendors, so their pricing is competitive," Terry said.

Using the FPGA, the company saved between $2 million and $5 million in nonrecurring engineering costs, as well as the "opportunity cost" of what would have been a two-year development cycle, Terry said.

"The motivation now to move to an ASIC is low," he said.

Even so, structured-ASIC players claim to be logging design wins at a robust pace. And despite projections that the segment will represent only a tiny slice of the overall ASIC market in five years, more players are joining the fray. Altera Corp. (San Jose) last year decided to augment its Stratix FPGA architecture with a structured-ASIC version called HardCopy Stratix. Flextronics Semiconductor Inc. (San Jose) is planning to launch a structured-ASIC service this year using technology licensed from eASIC Corp. (San Jose). And in January, startup Leopard Logic Inc. (Cupertino, Calif.) emerged with its Gladiator architecture, which is neither FPGA nor ASIC, but a hybrid of both.

As the midmarket battle intensifies, navigating the terrain is becoming a nightmare, said John East, chief executive of Actel Corp. (Sunnyvale, Calif.). "It starts with the fact that the way FPGA suppliers count gates is way different from the way ASIC suppliers count gates. So what you think you see is not what you get," he said.

What's more, not all structured ASICs are created equally.

"We prefer the term 'platform ASIC,' " said Keith Horn, vice president of Fujitsu Microelectronics America Inc. (Sunnyvale, Calif.), echoing the sentiments of such companies as LSI Logic Corp. (Milpitas, Calif.) and NEC Electronics Inc. (Santa Clara, Calif.). Platform, these suppliers say, denotes complexity as well as flexibility. The devices usually contain such elements as processors, serial transceivers or multiply-and-accumulate blocks. And because they employ leading-edge process technology, they offer higher density and speed, as well as a migration path to standard-cell designs.

"Structured ASIC implies something that is essentially flops, gates, memory and I/O," said Fujitsu's Horn. "When customers think of platform-based ASIC, they think of a structured ASIC that contains IP."

The difference is one of semantics, though the platform variety tends to serve more as an alternative to application-specific standard products than FPGAs, according to Jordan Selburn, an analyst at iSuppli Corp. (El Segundo, Calif.).

Which solution?

By any name, the question remains: Which one is most cost-effective for a given design? It used to be a rule of thumb that densities of more than 500,000 gates and volumes above 100,000 units were beyond the capability of FPGAs. Today, FPGAs approach ASIC-equivalent densities of 1 million gates, and shipments can reach 100,000 units. Indeed, some structured-ASIC designs are cost-effective at quantities as low as 3,000 units, said Vince Hopkin, vice president of digital ASICs at AMI Semiconductor Inc. (Pocatello, Idaho). The minimum-order quantity for Altera's Stratix HardCopy ASICs is 500 pieces, according to Don Faria, senior vice president of the company's application business group.

Chip suppliers offer help in the form of ROI calculators that factor in unit price, development time, tools cost, minimum order requirements, projected volume ramp and life span of the design. A more detailed analysis might include availability of supply, lead times, logistics and inventory costs.

In the case of ASICs, re-spins to correct flaws in the original design are a fact of life. To allow for this inevitability, OctigaBay's Terry suggests doubling the NRE in your ASIC budget to cover the cost of two mask sets and other manufacturing-related engineering expenses. Structured-ASIC NREs vary, but are generally in the range of $150,000 to $300,000.

While a customer may initially balk at an FPGA's $3,000 price tag, it could turn out to be reasonable after weighing ASIC costs, as well as time-to-revenue and other "hidden" variables, said Bill Latino, senior director of the global accounts team at Xilinx.

"In the automotive world where you may have 50 electronic control modules in a car, using an ASIC or custom microcontroller you'd have to inventory all 50 different modules, where with an FPGA you'd have to inventory only one module, because you can program the FPGA to [provide] many different features," Latino said. "Even though that module may be priced a few pennies higher, the customer saves on inventory cost."

Though he couldn't quantify the potential inventory cost savings, Latino said several leading automakers are looking at using FPGAs to simplify their inventory task and reduce the cost of manufacturing.

Another consideration is whether the design's cost will be reduced later by converting to some form of ASIC. If that is the case, add risk to the equation. The risk can take several forms. "Risk is 'who can I count on, whose silicon is going to work with the fewest re-spins, and will they still be in business in three years when I try to buy parts?' " said iSuppli's Selburn.

If an FPGA design doesn't work the first time, it may set your development schedule back a week or two, whereas an ASIC redesign can take months, and a re-spin of the silicon will cost an additional NRE. There is also production risk: Does your vendor have more than one manufacturing source?

If a design is targeted for a cell-based ASIC, customers may choose to lower their risk--through reducing development cost and time--by selecting a supplier that also has structured products. Indeed, risk reduction may be one of the most compelling benefits of structured ASICs, according to Selburn.

"That's the advantage companies like LSI, NEC and Fujitsu have over a pure structured-ASIC company, and it actually may prove to be an edge for those companies over companies that only have cell-based offerings," he said.

Altera may have a similar advantage in its low-risk migration path from FPGAs to structured ASICs, Selburn said.

"If the risk is very low, then going to a structured ASIC immediately would make a lot more sense because the customer can start saving a lot quicker," said AMI Semiconductor's Hopkin.

The good news is that there is a wealth of information available for minimal effort. A visit to any supplier's Web site can net pages and pages of product data and application notes. Some sites have provisions for submitting electronic requests for quotation. Distributor and manufacturers' representative contacts can also be found there.

With the exception of LSI Logic, which has trained its distributors to handle turnkey RapidChip platform ASIC designs, ASIC companies rely on manufacturers' representatives in combination with their own direct sales forces to identify design opportunities. Because ASIC engagements require dedicated engineering resources, the number of designs that suppliers can pursue is limited.

The distribution channel is an important component of the FPGA business model, handling not only value-added services and order fulfillment, but also augmenting suppliers' internal sales force to identify potential customers early in the system development phase. Often, the distributor is the primary liaison with the midtier customer throughout the engagement. This division of labor lets the supplier focus resources on supporting tier-one customers, which tend to have multiple concurrent projects, albeit the expertise level is the same, as are the support tools.

"We try to put real things in customers' hands they can work with," said Avnet's Ittel. For example, to support Xilinx customers, Avnet has developed reference designs, evaluation boards and hands-on laboratories where engineers can work with products, as opposed to hearing a marketing pitch.

The design chain

Suppliers of ASICs, with their advanced architectures and ASIC-like features, are engaging with customers earlier than ever before, in much the same way as FPGA suppliers, said Phil DeMarie, vice president of worldwide distribution at Altera. As FPGA features and capabilities have become more ASIC-like, so has the relationship between supplier and customer.

"In the early days, it was more of a socket sell," DeMarie said. "Today, given the complexity of FPGAs, it's important to be involved at the front end of the design, but also to understand what the customer is trying to achieve before we can come in with a solution. There are a lot of different functions our technology can do on a board, so the earlier we're engaged the more value we can bring to the customer."

"For instance, we now have the Nios microprocessor that, combined with our Cyclone FPGAs, in many cases can provide a lower-cost solution than if they used somebody else's microprocessor and our Cyclone device," said DeMarie. "We can often eliminate the cost of the microprocessor because we can embed it in our device."

It's fair to say that anyone undertaking a new design is also thinking about reducing cost down the road. Once you know your technology re-quirements, you can start to narrow the field of options. The lowest-risk path is FPGA, but if you think there may be an ASIC in your future, it's wise to do a detailed cost analysis up front.

"I think there's strong awareness across the engineering portion of the customer base on structured ASIC vs. FPGA vs. standard-cell ASIC," Horn said. "It's a great discussion point, because customers are making a conscious decision in which of those three directions to go."