TITLE      EE481 PAL Mod. 4 Counter Example
DATE       Oct. 8, 2003
REVISION   1.2
PATTERN    Alpha
Author     Lhamon
Company    U.K. 
CHIP DEVICE PALCE22V10H

; <- comment 
; Here is an example of a program for a resetable counter that
; counts from 0-4 inclusive.
; You can edit this file so that it implements what ever you    
; want.
;
; Also, remember that the flip-flops on the PAL are D flip-flops,
; you will have to convert your euqations if you designed        
; with T or JK excitations.                                      
;
; Note: The design need not be logically reduced since there are
; steps taken by the optimizer to reduce and simplify the equation.
; For example:  y = a*b + b  would be optimized to be   y = b;
; However, the compiler/optimizer cannot optimize your K-map since
; your entering boolean equations for the K-map.
;


;  Inputs  

Pin         1  clock
Pin         2  reset               ;1st digit in 4-bit no. 

;  Outputs  

Pin        14 Q0   REGISTERED    ; <- tells fitter that you want a FF
Pin        15 Q1   REGISTERED
Pin        16 Q2   REGISTERED
Pin        17 A13R REGISTERED
Pin        18 A13  COMB

EQUATIONS
; LOGIC EQUATIONS 

; a plan "=" is combinational assigment, basically the output of a gate
; a ":=" is an registered assigment where it is updated when clk goes high

;  /  is NOT
;  *  is AND       +  is  OR
; :*: is EXNOR    :+: is EXOR
Q0 := /reset * (/Q2 * /Q0)               ; LSB
Q1 := /reset * ((/Q1 * Q0) + (Q1 * /Q0))
Q2 := /reset * (Q1 * Q0)                 ; MSB

; A13R and A13 are high when counter = 1 or 3
A13   = /Q2 * /Q1 * Q0  +  /Q2 * Q1 * Q0 ; 
A13R := /Q2 * /Q1 * Q0  +  /Q2 * Q1 * Q0 ; 

; Note the differences in the simulation for A13 and A13R 
; A13R's output is delayed until the next rising edge of the clock
; where as A13 is not.
;

SIMULATION

TRACE_ON   clock  reset Q0 Q1 Q2 A13R A13 ;Variables to be simulated
setf       reset
CLOCKF     clock
CLOCKF     clock
setf       /reset
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock

CHECKQ    Q0 Q1 /Q2     ; check the values of the F/F

CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock
CLOCKF     clock       ; go through one full cycle of clock

TRACE_OFF