MODULE Counter3

TITLE 'Mike Lhamon'
" BCD Counter Example #3 of a state machine design.

" Nov. 13, 2003     EE481   University of Kentucky

" This example uses mathematical operators for the design entry
" Note: The output OUT is high for states (3,4,7) instead of (2,6) !!!!
" Also: Notice in the simulation how the output is formed after the rising
"       edge of the clock, and that the reset works both async and sync.

clock PIN;
reset PIN;

" Output pins
 a, b, c, d, out pin istype 'reg_D';
"a is the MSB,   d is the LSB 
Counter = [a,b,c,d];      " Defined a set,  (a bus structure)

x macro {.x.} ;       " Macro for dont care

" comment starts with a one, double quote
" not operator  !
" xor operator  $
" xnor operator !$
"  or operator  #
" and operator  &
" addition operator +
" combinational assignment
" registered assignment

equations

Counter.clk = clock;
out.clk = clock;
Counter.aclr = reset;
out.aclr = reset;
 
              "  NOTICE that this design is in dependent on number of bits.
              "      There is no state table so high counts can be achieved with
              "      little modification to design.
              "  Note the + symbol is addition
when ((Counter < 10) & (reset != 1)) then   Counter := Counter + 1;
else Counter := 0;

when (((Counter == 2)  # (Counter == 3) # (Counter == 6)) & (reset != 1)) then out:= 1;
else  out :=0;

" Same test vectors as in example #1 but it is organized better with sets
" Now dont care x takes on the length of the set
test_vectors
  ( [clock, reset]   -> [Counter] )
  [x, 1]   -> [x];
  [.c., 1] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 1]   -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [x, 1]   -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
  [x, 1]   -> [x];
  [.c., 0] -> [x];
  [.c., 0] -> [x];
END